The development of electronic devices with printed circuit boards typically involves many steps, known as a design flow. This design flow typically starts with a specification for a new circuit to be implemented with a printed circuit board. The specification of the new circuit can be transformed into a circuit design, such as a netlist, for example, by a schematic capture tool or by synthesizing a logical circuit design, sometimes referred to as a register transfer level (RTL) description of the circuit. The netlist, commonly specified in an Electronic Digital Exchange Format (EDIF), can describe nets or connectivity between various devices or instances in the circuit design.
The design flow continues by verifying functionality of the circuit design, for example, by simulating or emulating the circuit design and verifying that the results of the simulation or emulation correspond with an expected output from the circuit design. The functionality also can be verified by statically checking the circuit design for various attributes that may be problematic during operation of an electronic device built utilizing the circuit design.
Once the circuit design has been functionally verified, the design flow continues to design layout and routing, which includes placing and interconnecting various components into a representation of a printed circuit board. This procedure can be implemented in many different ways, but typically, through the use of a layout tool, which can allow a designer to drag or place parts from a library onto the printed circuit board. The layout tool can validate the electronic device and perform various design rule checks on placed parts to ensure that the electronic device can be effectively manufactured. The layout design for the printed circuit board can be included in file specified in an ODB++ (Open Database++) format, a Gerber-based format, or the like.
The design flow may perform one or more design for manufacturability (DFM) procedures on the layout design, which can determine whether the electronic device described in the layout design can be manufactured. The design for manufacturability procedures can include a design for fabrication (DFF) processes, a design for assembly (DFA) processes, a design for test (DFT) processes, or the like. The design for fabrication processes can determine whether a bare printed circuit board can be fabricated based on the layout design. The design for assembly processes can determine whether components can be disposed or coupled to the printed circuit board during assembly of the electronic device. The design for test processes can identify whether testing procedures can be utilized on manufactured electronic devices, for example, to detect process defects during assembly, perform electrical verification of a manufactured electronic device, or the like.
A design for manufacturing (DFM) tool can apply a set of constraints corresponding to manufacturing capabilities of the particular manufacturer to a layout design of the printed circuit board, and generate results that indicate where the layout design deviates from the set of constraints. Since the constraints are design-agnostic, many of the applied constraints may not be relevant to a particular layout design. The results therefore can include false-positives in the reports of deviations for the designer to manually review. Based on the review of the results, the designer can revise the layout design and re-apply the constraints, sometimes iteratively, until the designer achieves a layout design of the printed circuit board that can be manufactured by the particular manufacturer.
Some designers have attempted to reduce the burden associated with applying design-agnostic constraint sets by manually building constraint sets customized to the layout design for the design for manufacturing tool. This customized approach for performing design for manufacturing analysis is a time-consuming process often with extensive manual interaction with the design for manufacturing tool, such as manual generation of engineering rules file (ERF) models for each check in checklist. Since a single manufacturer can have hundreds of different factors, such as a final finish on the copper, a solder mask application, or the like, and technologies, such as a blind drill, buried drill, back drill, micro via, or the like, which can be utilized in the manufacture the printed circuit board assembly described by the layout design, the customized approach for performing design for manufacturing analysis becomes nearly impractical due to complexity arising from the number of factors and technologies to consider.
Many developers further have multiple different manufacturers or suppliers that they can utilize to manufacture the printed circuit board from the layout design. These developers typically perform the design for manufacturing analysis for a single manufacturer and then make the assumption that the resulting layout design can also be implemented by other manufacturers. As printed circuit board technology and associated manufacturing processes have become more sophisticated, the previous assumption of universal manufacturability has not held, resulting in reduction of yield and product quality.